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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
PM4354
COMET-QUAD
COMET-QUAD EVALUATOR BOARD DESIGN
PRELIMINARY ISSUE 2: JANUARY 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
PUBLIC REVISION HISTORY Issue No. 1 2 Issue Date Feb 2000 January 2001 Details of Change Document created. Revised Line Protection. Updated Schematics. Updated Layout. Updated BOM.
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
CONTENTS 1 INTRODUCTION...................................................................................... 1 1.1 1.2 1.3 2 3 PURPOSE..................................................................................... 1 SCOPE.......................................................................................... 1 APPLICATION............................................................................... 1
FEATURES .............................................................................................. 3 GENERAL DESCRIPTION OF THE COMET-QUAD EVALUATOR KIT .. 5 3.1 3.2 3.3 THE COMET-QUAD EVALUATOR KIT ......................................... 5 HARDWARE ................................................................................. 5 SOFTWARE .................................................................................. 5
4
BLOCK DESCRIPTION ........................................................................... 6 BLOCK DIAGRAM ................................................................................... 6 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 COMET-QUAD .............................................................................. 6 PCI BRIDGE.................................................................................. 9 SEEP............................................................................................. 9 OSCILLATORS ........................................................................... 10 TRANSMIT AND RECEIVE LINE INTERFACE ........................... 10 LINE TERMINATION ....................................................................11 PROTECTION CIRCUITRY .........................................................11 POWER SUPPLY........................................................................ 13 PCI EDGE CONNECTOR ........................................................... 14 BACKPLANE BUS CONNECTOR .............................................. 14
5
DESIGN ISSUES ................................................................................... 16
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
5.1
COMET-QUAD DESIGN CONSIDERATIONS ............................ 16 5.1.1 POWER SUPPLY ............................................................. 16 5.1.2 DECOUPLING .................................................................. 16 5.1.3 INTERNAL FDL TRANSMITTER ...................................... 16 5.1.4 INTERNAL DATA LINK RECEIVER.................................. 17 5.1.5 PER-CHANNEL SERIAL CONTROLLERS....................... 17 5.1.6 T1/E1 FRAMER LOOPBACK MODES ............................. 17
5.2
PCI BRIDGE................................................................................ 18 5.2.1 DUAL ENVIRONMENT COMPLIANCE ............................ 18 5.2.2 PCI 9050 INITIALIZATION ............................................... 18 5.2.3 INTERNAL REGISTER ACCESS ..................................... 19 5.2.4 DIRECT DATA TRANSFER MODES ................................ 19
5.3 5.4 5.5 5.6 6
LINE PROTECTION.................................................................... 19 JUMPER CONFIGURATION....................................................... 20 POWER ESTIMATES ................................................................. 20 VOLTAGE REGULATORS - CURRENT AND THERMAL CALCULATIONS ......................................................................... 21
PHYSICAL AND MECHANICAL DESCRIPTIONS ................................. 24 6.1 FORM FACTOR .......................................................................... 24 6.1.1 FACE PLATE .................................................................... 26 6.2 CONNECTORS ........................................................................... 27 6.2.1 LINE INTERFACE CONNECTORS .................................. 27 6.2.2 SYSTEM BUS CONNECTOR .......................................... 27 6.2.3 PCI EDGE CONNECTOR ................................................ 27
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
6.3
LEDS ........................................................................................... 27 6.3.1 COMET-QUAD INTERRUPT LED .................................... 27 6.3.2 POWER STATUS LEDS................................................... 27
7
SOFTWARE INTERFACES ................................................................... 28 7.1 7.2 MEMORY MAP............................................................................ 28 PCI 9050 CONFIGURATION....................................................... 28
8 9
CONFORMANCE SPECIFICATION ...................................................... 31 LAYOUT DESCRIPTION ....................................................................... 32 9.1 9.2 9.3 9.4 9.5 COMPONENT PLACEMENT ...................................................... 32 LAYER STACKING AND TRANSMISSION LINE IMPEDANCE CONTROL................................................................................... 33 POWER AND GROUND ............................................................. 36 PCI BUS SIGNAL SPECIFICATION............................................ 37 ROUTING.................................................................................... 38
10 11 12 13 14
GLOSSARY ........................................................................................... 39 REFERENCES....................................................................................... 41 DISCLAIMER ......................................................................................... 42 APPENDIX A: BILL OF MATERIALS ..................................................... 43 APPENDIX B: SCHEMATICS ................................................................ 47 14.1 14.2 14.3 14.4 14.5 ROOT DRAWING, SHEET 1 ....................................................... 47 COMET-QUAD BLOCK, SHEET 2 .............................................. 47 LINE INTERFACE, SHEET 3 AND 4 ........................................... 47 PCI INTERFACE, SHEET 5 ........................................................ 47 POWER, SHEET 6...................................................................... 47
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COMET-QUAD EVALUATOR BOARD
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APPENDIX C: LAYOUT ......................................................................... 48
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PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
LIST OF FIGURES FIGURE 1: WIRELESS BASE STATION APPLICATION.................................... 2 FIGURE 2: V5.2 INTERFACE APPLICATION .................................................... 2 FIGURE 3: BLOCK DIAGRAM ........................................................................... 6 FIGURE 6: EXTERNAL ANALOG INTERFACE CIRCUIT FOR ONE CHANNEL 12 FIGURE 7: SYSTEM BUS CONNECTORS...................................................... 15 FIGURE 8: PCI UNIVERSAL 32-BIT CARD MECHANICAL OUTLINE ............ 24 FIGURE 9: PCI UNIVERSAL 32-BIT CARD EDGE CONNECTOR DIMENSIONS AND TOLERANCES ......................................................................................... 26 FIGURE 10- FACE PLATE ............................................................................... 26 FIGURE 12: MAIN COMPONENT PLACEMENT DIAGRAM............................ 33 FIGURE 13: LAYER STACK ............................................................................. 34 FIGURE 14: PCB CROSS SECTION ............................................................... 34 FIGURE 15: GND PLANE ................................................................................ 36 FIGURE 16: VCC PLANE ................................................................................. 36 FIGURE 17: 2.5V PLANE ................................................................................. 37 FIGURE 18: 3.3V PLANE ................................................................................. 37
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COMET-QUAD EVALUATOR BOARD
LIST OF TABLES TABLE 1 PCI9050 LOCAL ADDRESS SPACE ALLOCATION............................ 9 TABLE 2: RJ-48C PINOUT ............................................................................... 10 TABLE 5: EXTERNAL COMPONENTS DESCRIPTION................................... 13 TABLE 6: COMET-QUAD LOOPBACK MODES .............................................. 18 TABLE 7: POWER ESTIMATES....................................................................... 20 TABLE 8: SYSTEM MEMORY MAP ................................................................. 28 TABLE 9: PCI LOCAL ADDRESS SPACE REGISTER..................................... 28 TABLE 10: PCI LOCAL ADDRESS SPACE ...................................................... 28 TABLE 11: PCI LOCAL ADDRESS SPACE RE-MAP ....................................... 29 TABLE 12: PCI LOCAL ADDRESS SPACE REGION DESCRIPTORS ............ 29 TABLE 13: PCI CHIP SELECT BASE............................................................... 29 TABLE 14: PCI LOCAL ADDRESS SPACE REGISTERS ................................ 30 TABLE 15: PCB PARAMETERS....................................................................... 35 TABLE 16: MAJOR COMPONENTS LIST........................................................ 43 TABLE 17: BILL OF MATERIALS ..................................................................... 43
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COMET-QUAD EVALUATOR BOARD
1
INTRODUCTION The COMET-QUAD Evaluator Board is part of the COMET-QUAD Evaluator Kit and allows for the evaluation and demonstration of PMC-Sierra's PM4354 COMET-QUAD device. It also provides a platform for the development and integration of software. The COMET-QUAD Evaluator Board is configured, monitored, and powered through the PCI edge connector. Software drivers are available from PMCSierra, Inc. to fully control and utilize the COMET-QUAD Evaluator Board.
1.1
Purpose The COMET-QUAD Evaluator Board is designed to assist engineers in designing their products using PMC-Sierra's COMET-QUAD device. The purpose of this document, hence, is to provide a detailed hardware specification for the COMETQUAD Evaluator Board. The specification detailed here is sufficient to allow design implementation and verification.
1.2
Scope This document describes the design for the COMET-QUAD Evaluator Board. A general description of the device is given, along with a block diagram for the design. A description for each of the functional blocks of the design is given followed by a detailed account of design issues, including physical and mechanical descriptions, implementation descriptions and layout.
1.3
Application The COMET-QUAD device is suitable in the following applications: * * * * * * T1/E1 Wireless Digital Loop Carriers (DLC's) and Cellular Base Stations T1/E1 Internet Access Equipment T1/E1 Channel Service Units (CSU) T1/E1 Frame Relay Interfaces T1/E1 ATM Interfaces T1/E1 Multiplexers (CPE MUX)
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
* * * *
Digital Private Branch Exchanges (PBX) Digital Access Cross-Connect Systems (DACS) and Electronic DSX CrossConnect Systems (EDSX) ISDN Primary Rate Interfaces (PRI) Test Equipment
Figure 1 illustrates the COMET-QUAD device in a wireless base transceiver station (BTS) application and Figure 2 illustrates the device in a V5.2 Interface Application. Figure 1: Wireless Base Station Application
PM4354 COMET-QUAD Software Selectable T1/E1/J1 Framer T1/E1/J1 Longhaul/ Shorthaul LIU PM4354 COMET_QUAD Tx/Rx RF Subsystem Intel or Motorola P
DS3 or Fibre Optics
PM8313 D3MX or PM5342 SPECTRA
Basestation Switch Fabric
PM4354 COMET-Quad PM4354 COMET-Quad PM4354 COMET-Quad PM4354 COMET-Quad
CDMA/TDMA/GSM
Base Transceiver Station
G G G
Public Switched Telephone Network
Base Station Controller
Figure 2: V5.2 Interface Application
Linecard Linecard
PM5 34 2 SPEC TRA -1 55
PM5 36 2 TUPP+
Swi tch Fabric
T 1/E1/J1 F ramer
T1/E1/J1 L H/SH LIU
PM4354 COMET-Qu ad
V 5.2
4 x E1 Bundle
T 1/E1/J1 LH/SH LIU
T1/E1/J1 F ramer
Switch Fabric
G G G
PM4354 COMET-Quad
P
Linecard PM7364 F REE DM-32
PM 4354 COM ET-Q ua d
Intel o r Motor ola
P
PM7364 FREE DM-32
PM 4354 COM ET-Q ua d PM 4354 COM ET-Q ua d
Access Conce ntrator
Centra l Office Switch
Subs cribers
S TM-1
G
G
G
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COMET-QUAD EVALUATOR BOARD
2
FEATURES General * * * PCI Interface - allows for microprocessor access to the COMET-QUAD via a host PC Provides a platform for the demonstration of the COMET-QUAD's functions and performance. Provides software-selectable E1, T1, J1 rate selection.
T1 Mode * * * * * * * Interface to 4 short haul and long haul T1 lines Frames to ESF and SF formats Integral HDLC controller for Facilities Data Link Support Serial PCM interfaces to each framer to support 1.544 Mbit/s ingress/egress system interfaces Detect loss of signal, pulse density violation, Red alarm, Yellow alarm, and AIS alarm Performance monitoring with accumulation of CRC-6 errors, framing bit errors, line code violations, and loss of frame events Provides synchronous backplane systems 8Mbit/s H-MVIP interfaces for access channel associated signaling (CAS) and common channel signaling (CCS) for each line Per channel payload loopback Automatic gain control to accommodate distances with up to 36 dB of cable attenuation at nominal conditions using PIC 22 gauge cable emulation Programmable Line build outs of DSX-1 as well as CSU of -7.5dB, -15dB and -22dB Line interface capable of generating G.703 wave shapes for 100 T1 lines
* * * *
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
*
Provides a programmable PRBS test pattern generator, receiver and analyzer.
E1 Mode * * * * * * Interface to 4 short haul and long haul E1 lines Frames to FAS, CAS and CRC-4 formats Integral HDLC controller for Facilities Data Link Support Detect loss of signal, loss of frame, loss of signaling multiframe and loss of CRC Performance monitoring with accumulation of CRC-4 errors, far end block errors, framing bit errors, and line code violation Provides synchronous backplane systems 8Mbit/s H-MVIP interfaces for access channel associated signaling (CAS) and common channel signaling (CCS) for each line Per channel payload loopback Automatic gain control to accommodate distances with up to 36 dB of cable attenuation at nominal conditions using PIC 22 gauge cable emulation Line interface capable of generating G.703 wave shapes for 120 E1 lines Provides a programmable PRBS test pattern generator, receiver and analyzer.
* * * *
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
3 3.1
GENERAL DESCRIPTION OF THE COMET-QUAD EVALUATOR KIT The COMET-QUAD Evaluator Kit The COMET-QUAD Evaluator Kit is a self-contained hardware and software reference design tool, designed to operate on a Pentium-based PC running Windows 95/98/2000/NT. The kit provides a platform for the engineers to develop and integrate software with a state-of-the-art T1/E1/J1 design.
3.2
Hardware The kit is supplied with a 4 channel COMET-QUAD Evaluator Board that has been developed to fit into a PCI-based desktop computer. This board consists of a PM4354 COMET-QUAD device, the necessary interface circuitry, magnetics, and line protection for long haul and short haul operation in either T1 or E1 mode. The board is configured, monitored, and powered through the PC's motherboard.
3.3
Software The kit contains an interactive program, complete with a graphical user interface (GUI), and a set of scripts to configure the COMET-QUAD device. The software, installed from the kit's CD-ROM, provides a visual interface to control and monitor the COMET-QUAD functions. Direct access to the COMET-QUAD device is provided to read or write any of the COMET-QUAD registers, perform a hardware reset of the COMET-QUAD, and observe the status of the hardware interrupt pin of the COMET-QUAD.
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
4 4.1
BLOCK DESCRIPTION Block Diagram The following section describes in detail the function of each hardware block shown in Figure 3. Figure 3: Block Diagram PMC-Sierra, INC. COMET-QUAD Evaluation Board
Protection Circuitry Transformer Protection Circuitry
2.048 MHz Osc
RJ48C
Connector COMETQUAD Backplane
RJ48C
Protection Circuitry
Transformer
Protection Circuitry
RJ48C
Protection Circuitry
Transformer
Protection Circuitry
PM4354 COMETQUAD
Micro Interface
RJ48C
Protection Circuitry
Transformer
Protection Circuitry
PCI Bridge
SEEP
LEDs
4.2
COMET-QUAD The PM4354 Four Channel Combined E1/T1/J1 Transceiver and Framer (COMET-QUAD) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1, J1 and E1 systems with a minimum of external circuitry. The COMET-QUAD is software configurable, allowing feature selection without changes to external wiring. Analog circuitry is provided to allow direct reception of long haul E1 and T1 compatible signals with up to 36 dB cable loss (at 1.024 MHz in E1 mode) or up
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
to 36 dB cable loss (at 772 kHz in T1 mode) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. The COMET-QUAD recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to SF and ESF signal formats. In E1 mode, the COMET-QUAD frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported. The COMET-QUAD supports detection of various alarm conditions such as loss of signal, pulse density violation, Red alarm, Yellow alarm, and AIS alarm in T1 mode and loss of signal, loss of frame, loss of signaling multiframe and loss of CRC multiframe in E1 mode. The COMET-QUAD also supports reception of remote alarm signal, remote multiframe alarm signal, and alarm indication signal in E1 mode. The presence of Yellow and AIS patterns in T1 mode and remote alarm and AIS patterns in E1 mode is detected and indicated. In T1 mode, the COMET-QUAD integrates Yellow, Red, and AIS alarms as per industry specifications. In E1 mode, the COMET-QUAD integrates Red and AIS alarms. Performance monitoring with accumulation of CRC-6 errors, framing bit errors, line code violations, and loss of frame events are provided in T1 mode. In E1 mode, CRC-4 errors, far end block errors, framing bit errors, and line code violation are monitored and accumulated. The COMET-QUAD provides one receive HDLC controller per channel for the detection and termination of messages in the ESF facility data link (T1), national use bits (E1), or in any arbitrary timeslot (T1 or E1). In T1 mode, the COMETQUAD also detects the presence of in-band loop back codes and ESF bit oriented codes. Detection and optional debouncing of the 4-bit Sa-bit codewords defined in ITU-T G.704 and ETSI 300-233 is supported. An interrupt may be generated on any change of state of the Sa codewords. Dual (transmit and receive) elastic stores for slip buffering and rate adaptation to backplane timing are provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a per-channel basis. Receive side data and signaling trunk conditioning is also provided. In T1 mode, the COMET-QUAD generates framing for SF and ESF formats. In E1 mode, the COMET-QUAD generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled. Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1 compatible signals using a minimum of external components. Typically,
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
only line protection, a transformer and an optional line termination resistor are required. Digitally programmable pulse shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into 120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements. In the transmit path, the COMET-QUAD supports signaling insertion, idle code substitution, digital milliwatt tone substitution, data inversion, and zero code suppression on a per-channel basis. Zero code suppression may be configured to Bell (bit 7), GTE, or DDS standards, and can also be disabled. Transmit side data and signaling trunk conditioning is also provided. Signaling bit transparency from the backplane may be enabled. The COMET-QUAD provides one transmit HDLC controller per channel. These controllers may be used for the transmission of messages in the ESF data link (T1), national use bits (E1), or in any timeslot (T1 or E1). In T1 mode, the COMET-QUAD can be configured to generate in-band loop back codes and ESF bit oriented codes. In E1 mode, transmission of the 4-bit Sa codewords defined in ITU-T G.704 and ETSI 300-233 is supported. To provide for V5 applications where up to three HDLC channels are contained in each E1, the COMET-QUAD provides a CCS H-MVIP interface. This interface allows the HDLC channels to be inserted or extracted for external processing. Each channel of the COMET-QUAD can generate a low jitter transmit clock from a variety of clock references, and also provides jitter attenuation in the receive path. A low jitter recovered T1 clock can be routed outside the COMET-QUAD for network timing applications. Serial PCM interfaces to each T1/E1 framer allow 1.544 Mbit/s or 2.048 Mbit/s backplane receive/backplane transmit system interfaces to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic. For synchronous backplane systems, 8.192 Mbit/s H-MVIP interfaces are provided for access to PCM data, channel associated signaling (CAS) and common channel signaling (CCS) for each T1 or E1. The CCS signaling H-MVIP interface is independent of the 64 Kbit/s PCM and CAS H-MVIP access. The use of the H-MVIP interface requires that common clocks and frame pulse be used along with T1/E1 elastic stores.
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
The COMET-QUAD is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be masked and acknowledged through the microprocessor interface. For a complete description of the COMET-QUAD, please refer to PMC-Sierra's COMET-QUAD data sheet, PMC-1990315 [1]. 4.3 PCI Bridge The PCI Bridge used is PLX Technology's PCI9050 PCI Bus Target Interface Chip. The PCI9050 provides a target only interface, and as such does not initiate PCI bus transactions. The PCI9050 has a 16 long word write FIFO and 8 long word read FIFO allowing the PCI bus to burst data to and from the COMET-QUAD. The local address space is configured to be 32-bit non-multiplexed, big endian, non-burst, and nonprefetchable. Even though the COMET-QUAD has only an 8-bit data bus, the PCI9050 is configured as a 32-bit data bus. This was done to simplify the hardware design. Prefetching is not possible in this application because the COMET-QUAD has a number of registers with read side affects (e.g. interrupt status registers). The local bus is clocked at 33MHz by looping the buffered PCI clock output (BCLKO) available from the PCI9050 back to the local bus clock input. The local address spaces are allocated in the following fashion: Table 1 PCI9050 Local Address Space Allocation Address Space 0 1 2 3 unused unused unused Function COMET-QUAD Registers
Please refer to the PCI9050 datasheet [5] for more information. 4.4 SEEP The NM93CS46 Serial EEPROM from National Semiconductor is used to store configuration information for the PCI9050 bridge. This specific SEEP (or
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
equivalent) is required by PCI9050 because it supports sequential read operations. The SEEP is 1Kbit deep, 800 bits of which are occupied by the PCI9050 configuration data, leaving 224 bits (28 bytes) unused. Refer to the PCI9050 datasheet [5] for information on the format of the configuration data stored in the SEEP. 4.5 Oscillators The COMET-QUAD can run in either T1 or E1 mode. In T1 mode, oscillator Y1 should be populated with a 1.544 MHz oscillator. In E1 mode, oscillator Y1 should be populated with a 2.048 MHz oscillator. The COMET-QUAD can also optionally run in T1 mode with a 2.048 MHz oscillator. 4.6 Transmit and Receive Line Interface A transmit and receive line interface is required for each of the 4 channels. Each transmit and receive line interface consists of line connectors, line protection circuitry and magnetics. The magnetics used on this design is a quad package that contains both a receive and transmit transformer. Both the receive and transmit transformers have a 1:2.42 turns ratio with the "1" always on the chip side. Please refer to Table 16 for a list of manufacturers. The evaluator board provides one set of line interface connectors, a RJ-48C, for the receive and transmit of T1/E1 signals to and from the COMET-QUAD device for each channel. The RJ48C has been provided according to the ANSI T1.403 standard for a Universal Service Ordering Code (USOC) connector. Table 2 below details the pinout for the RJ-48C connector. Table 2: RJ-48C Pinout Pin 1 2 3 4 5 Signal RXRING RXTIP N.C. TXRING TXTIP
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
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COMET-QUAD EVALUATOR BOARD
6 7 8 4.7
N.C. N.C. N.C.
Line Termination The line interface provides one termination scheme for both T1 and E1 rates. A termination of 110 is used to allow the interface to be compatible with both 100 T1 and 120 E1. This provides a software switchable reference board for both T1 and E1 by simply configuring the COMET-QUAD device.
4.8
Protection Circuitry The protection circuitry prevents damage to telecommunications equipment caused by over-voltage and over-current power surges due to lightning strikes and AC power cross disturbances. The circuit is composed of two sections. The primary circuit protection consists of circuit protection for digital transmission equipment. The circuit is a proven solution that is currently used in the industry today. The configuration has passed Bellcore GR 1089-CORE, FCC Part 68 and UL 1459 & 1950. The TECCOR F1250T Telelink Fuse used in combination with the TECCOR P1800SC SIDACtor and P0720SC SIDACtor provide a solution for the regulatory requirements without the use of any additional series resistance. The two fuses provide over current protection and the three SIDACtors provide over voltage protection. The SIDACtors provide transient over voltage protection. In the standby mode, the device exhibits high off-state impedance eliminating excessive leakage currents and appears transparent to the circuits they protect. When the voltage across the device exceeds the switching voltage, SIDACtors will crowbar and simulate a short circuit. During this state, current gets driven into the ground, thereby reducing some of the voltage that shows across the transformer and eventually at the equipment. The device stays in this state until the current flowing through the SIDACtor falls below the holding current of the device. When this occurs, the device resets and returns to its' high off-state impedance. Secondary protection is provided using a combination of transformers and a diode array. The quad transformer with diode array module from Pulse further clamps any voltages.
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
The transformers provide 1500Vrms line isolation and serves to impedance match the lines to the transceiver line interface. Any remaining high positive or high negative voltage signals are further clamped by the diode array configuration. If the positive voltage signal is larger than the reference voltage plus the diode voltage, then the top diode becomes forward biased and steers the excess voltage into the power supply. If the negative voltage signal exceeds the diode voltage, then the bottom diode becomes forward biased and directs the excess negative voltage signals to ground. The transformer with diode array module chosen for this application is a quad package that contains one set of receive and transmit transformer and diode array for each of the four channels. Figure 6 shows an external protection circuit for designs required to meet major surge immunity and electrical safety standards including Bellcore GR 1089CORE, FCC Part 68 and UL 1459 & 1950. This circuit uses a part from Pulse that combines eight transformers (4 transmit and 4 receive) and the diode array module (equivalent to the diode array provided by Semtech) into a single module. This is an alternative way of implementing the circuit while reducing the number of required components. Figure 6: External Analog Interface Circuit for One Channel
VDD U1
TXTIP1 TXTIP2
Rt1
GND
1 : 2.42
Z1 P1800SC
F1250T TTip F1
TXREF
C1
Z5 P0720SC Z2 P1800SC GND GND F1250T TRing F2
TXRING1 TXRING2
Rt2
ATB
GND
RXTIP
1 : 2.42
Z3 P1800SC Rterm Z6 P0720SC Z4 P1800SC
F1250T RTip F3
GND F1250T RRing F4
RXRING
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Table 5: External Components Description Component Rt1 & Rt2 Rterm Description Typically 12.7 1% Resistors 18.2 1% Resistor for T1 & 120 E1 13 1% Resistor for 75 E1 (assuming a 1:2.42 transformer) 4.7F10% Capacitor Surge Resistant, Time Lag Fuse Bi-directional Transient Surge Protectors Bi-directional Transient Surge Protectors Surge Protector Diode Array Generally 1:2.42CT Transformers F1250T Telelink P1800SC P0720SC SRDA3.3-4 50436 (single) T1137 TG23-1505NS (single) TG23-1505N1 (dual) U1 (replaces both D1 and T1 & T2) Combined 1:2.42CT Transmit (quantity=4) and Receive (quantity=4) Transformers and Surge Protector Diode Array T9021 Pulse Teccor Teccor Teccor Semtech Midcom Pulse Halo Halo Part Number Source
C1 F1 - F4 Z1 - Z4 Z5, Z6 D1 T1&T2
4.9
Power Supply The COMET-QUAD evaluator design contains components that operate at 2.5V, 3.3V, or 5V, referenced to ground. The 5V supply is provided to the board through the PCI connector. The 2.5V and 3.3V supply is generated on the board via DC-DC voltage regulators.
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It is recommended that 5V power is provided before both 2.5V and 3.3V power to avoid device latchup. Please refer to the COMET-QUAD datasheet [1] for further details of powering up the COMET-QUAD device. 4.10 PCI Edge Connector The PCI Edge Connector has been implemented as a standard Universal, 32 bit PCI connector. The system board designer must leave all reserved and Vio pins unconnected as voltage rail safety precautions. The universal expansion board is capable of detecting the signaling environment in use, and adapting itself to that environment accordingly. It can be plugged into either 3.3V or 5.0V connector type. 4.11 Backplane Bus Connector The Backplane bus connectors, as shown in Figure 7, provide system side serial clock and data access as well as H-MVIP access for up to four T1 or E1 streams to the COMET-QUAD. This is provided to allow for easy access to the backplane signals. By simply connecting across the jumpers(connecting pins 1 to 2, 3 to 4, etc), the backplane channel connectors also allow for easy configuration of external payload loopback. The H-MVIP backplane connectors, on the other hand, provide useful input/output test ports for testing the system signals. Note that when in H-MVIP mode, BTPCM[1] and BRPCM[1] act as CASBTD and CASBRD respectively.
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Figure 7: System Bus Connectors
J11
COMET-QUAD Backplane Channel#1 1 2 BTCLK[1] BTSIG[1] BTFP[1] BTPCM[1]/ CASBTD 7 8
COMET-QUAD Backplane Channel#2 1 2 J8 BRCLK[2] BRSIG[2] BRFP[2] BRPCM[2] 7 8 BTCLK[2] BTSIG[2] BTFP[2] BTPCM[2]
BRCLK[1] BRSIG[1] BRFP[1] BRPCM[1]/ CASBRD
COMET-QUAD Backplane Channel#3 1 2 J10 BRCLK[3] BRSIG[3] BRFP[3] BRPCM[3] 7 8 BTCLK[3] BTSIG[3] BTFP[3] BTPCM[3]
J9
COMET-QUAD Backplane Channel#4 1 2 BTCLK[4] BTSIG[4] BTFP[4] BTPCM[4] 7 8
BRCLK[4] BRSIG[4] BRFP[4] BRPCM[4]
COMET-QUAD H-MVIP Backplane 1 2 J12 GND GND CMVFPB CMVFPC 7 8 CCSBTD MVBTD MVBRD_CCSBRD CMV8MCLK
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5
DESIGN ISSUES The following sections describe design considerations of the evaluator board.
5.1
COMET-QUAD Design Considerations
5.1.1 Power Supply Analog power pins must be applied after VDD or they must be current limited to the maximum latch-up current of 100mA. A simple solution is to use a small filtering network between the VDD and the analog power pins to delay power to each AVD pin. 5.1.2 Decoupling A 0.01F capacitor is required for every two digital power pins, placed between alternating power and ground. A 0.1F capacitor required for every two digital power pins, placed between alternating power and ground. The capacitors should be placed as close to the actual pin as possible. The AVD pins require a filtering network between the GND plane and the 3.3V plane. The network is a single RC network with the resistor between the 3.3V plane and the AVD pin and the capacitor from the AVD pin to the GND plane. Please refer to the schematics and bill of materials for component values. 5.1.3 Internal FDL Transmitter It is important to note that access rate to the TDPR registers is limited by the rate of the XCLK crystal clock input. Consecutive accesses to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register should be accessed (with respect to WRB rising edge and RDB falling edge) at a rate no faster than the XCLK clock rate. (In T1 mode with a 2.048 MHz XCLK reference, accesses should be no faster than XCLK x 193/256.) This time is used by XCLK to sample the event, write the FIFO, and update the FIFO status. Instantaneous variations in the XCLK clock frequency (e.g. jitter in XCLK) must be considered when determining the procedure used to read and write the TDPR registers. Upon reset of the COMET-QUAD, the TDPR should be disabled by setting the EN bit in the TDPR Configuration Register to logic 0 (default value). An HDLC all-ones idle signal will be sent while in this state. The TDPR is enabled by setting the EN bit to logic 1. The FIFOCLR bit should be set and then cleared to initialize the TDPR FIFO before the TDPR is ready to transmit.
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5.1.4 Internal Data Link Receiver It is important to note that the access rate to the RDLC registers is limited by the rate of the XCLK crystal clock input. Consecutive accesses to the RDLC Status and RDLC Data registers should be accessed (with respect to WRB rising edge and RDB falling edge) at a rate no faster than 8/10 that of the XCLK clock rate. (In T1 mode with a 2.048 MHz XCLK reference, accesses should be no faster than XCLK x (193 x 8)/2560.) This time is used by XCLK to sample the event and update the FIFO status. Instantaneous variations in the XCLK clock frequency (e.g. jitter in XCLK) must be considered when determining the procedure used to read RDLC registers. On power up of the system, the RDLC should be disabled by setting the EN bit in the Configuration Register to logic 0 (default value). The RDLC Interrupt Control register should then be initialized to enable the INTB output and to select the FIFO buffer fill level at which an interrupt will be generated. If the INTE bit is not set to logic 1, the RDLC Status register must be continuously polled to check the interrupt status (INTR) bit. 5.1.5 Per-Channel Serial Controllers Proper initialization of the internal registers must be performed to eliminate erroneous control data from being produced on the outputs of the TPSC (RPSC) block. The output control streams should be disabled by setting the PCCE bit in the TPSC (RPSC) Configuration Register to logic 0. Then, all 96 locations of the TPSC (RPSC) must be filled with valid data. Finally the output streams can be enabled by setting the PCCE bit in the TPSC (RPSC) Configuration Register to 1. Direct access mode to the TPSC or RPSC is not used in the COMET-QUAD. However, direct access mode is selected by default whenever the COMETQUAD is reset. The IND bit within the TPSC and RPSC Configuration Registers must be set to logic 1 after a reset is applied. 5.1.6 T1/E1 Framer Loopback Modes The COMET-QUAD provides four loopback modes to aid in network and system diagnostics. The network loopbacks (Payload and Line) can be initiated at any time via the P interface, but are usually initiated once an inband loopback activate code is detected. The system Diagnostic Digital loopback can be initiated at any time by the system via the P interface to check the path of system data through the framer. The Per-DS0 loopback permits the payload to be looped-back on a per-DS0 basis to allow network testing without taking an entire link off-line. Please refer to Table 6 for a summary of the loopback
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operations. Note that only one of Payload Loopback, Line Loopback and Diagnostic Digital Loopback can be enabled at any one time. Table 6: COMET-QUAD Loopback Modes Loopback Mode Line Loopback Payload Loopback Per-Channel Loopback Per-Channel Loopback Diagnostic Digital Loopback 5.2 PCI Bridge Addr 00AH,10AH, 20AH,30AH 00AH,10AH, 20AH,30AH 06FH,16FH, 26FH,36FH 06CH,16CH, 26CH,36CH 00AH,10AH, 20AH,30AH Register Master Diagnostics Register Master Diagnostics Register TPSC Internal Register TPSC Configuration Register Master Diagnostics Register Bit LINELB PAYLB LOOP PCCE DDLB Set Logic 1 Logic 1 Logic 1 Logic 1 Logic 1
5.2.1 Dual Environment Compliance The PCI-9050 must use I/O buffers that can be compliant with either the 5.0V or 3.3V signaling environment. While there are multiple buffer implementations that can achieve this dual environment compliance, it is intended that they be dual voltage buffers - i.e. capable of operating from either power rail. They should be powered from "I/O" designated power pins on PCI connectors that will always be connected to the power rail associated with the signaling environment in use. This means that in the 5.0V signaling environment, these buffers are powered on the 5.0V rail. When the board is plugged into a 3.3V connector, these buffers are powered on the 3.3V rail. This enables the COMET-QUAD Evaluator Board to be compliant with either signaling environment. 5.2.2 PCI 9050 Initialization The PCI-9050 is used in the Evaluator Board to provide a compact high performance PCI bus target (slave) interface to the PCI bus. During power up, the PCI RST# signal resets the default values of the PCI 90501 internal registers. In return, the PCI 9050 outputs the local reset signal (LRESET#) and checks for the existence of the serial EEPROM. If a serial EPROM is installed, and the first 16-bit word is not FFFF, the PCI 9050 loads the
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internal registers from the serial EEPROM. Otherwise, default values are used. The PCI 9050 configuration registers can be written only by the optional serial EEPROM or the PCI host processor. During the serial EEPROM initialization, the PCI 9050 response to PCI target accesses is RETRYs. 5.2.3 Internal Register Access The PCI 9050 chip provides several internal registers, allowing maximum flexibility in bus interface design and performance. All of the PCI and the local configuration registers are accessible from the PCI bus and EEPROM. 5.2.4 Direct Data Transfer Modes The PCI host processor can directly access devices on the local bus for reads and writes. Configuration registers within the PCI 9050 control decoding and remapping of these accesses to local address space. 5.3 Line Protection Line protection circuitry is implemented to protect the Evaluator Board from damage caused by over-voltage and over-current power surges due to lightning strikes and power cross disturbances. Using the combination of the F1250T Telelink fuse, the P1800SC SIDACtor and the P0720SC SIDACtor eliminates the need for additional series line resistance. The elimination of the additional resistance allows the signal to maintain its' integrity. The resistance of the F1250T Telelink fuse is 0.109 15%. The low resistance results in negligible signal degradation, which allows the signal to remain within the required pulse shape template. Another advantage resulting from the removal of additional series line resistance is that it enables longer loop lengths. Adding the F1250T fuse is an economical solution. The fuse eliminates the need for costly power resistors and PTCs. Adding the P1800SC and P0720SC SIDACtors results in absolute surge protection regardless of the available surge current and the rate of applied voltage (dV/dt). The SIDACtor also can not be damaged by voltage, eliminates hysteresis and heat dissipation typically found with a clamping device, eliminates voltage overshoot caused by fast rising transients, and has negligible capacitance. The fuse is robust enough to live through lightning surges without causing unwanted openings, but interrupts correctly during situations involving power cross. The P1800SC SIDACtors are chosen because of the switching voltage of 220V.
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The diode array protects high-speed data interfaces from over voltages caused by ESD (electrostatic discharge), EFT (electrical fast transients), and lightning. During transient conditions, the diodes steer the transient to either the positive side of the power supply line or to the ground. The TVS diode used in the array is very important because it prevents over voltage on the power line, thereby protecting components that exist further down the line. Also, the capacitance of the diode array from Semtech has a very low capacitance (<15pF). Since the driving capacity of the transmitter can not handle a large load, this diode array is very suitable. The combination of the transformers and a built in diode array from Pulse was chosen because they have made a diode array obtaining low capacitance. 5.4 Jumper Configuration Jumpers are used at the system bus connector to manually configure external payload loopback of the Evaluator Board. 5.5 Power Estimates Table 7: Power Estimates Power (Watts) +2.5V COMET-QUAD +3.3V COMET-QUAD 2.5V Regulator +5V PLX 9050 MAX 701 74HC08 NM93CS46 (EEPROM) Misc 0.650 0.005 0.005 0.005 1 130 1 1 1 200 1.7 1.5 500 160 0.300 120 Current (mA)
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TOTAL
1.665
333
5.6
Voltage Regulators - Current and Thermal Calculations Power Dissipation in the Regulators: For 2.5V Regulator: Using worst case, Vin = 3.3 + 5% = 3.465V Vout = 2.5 - 2% = 2.45V Iout = 160mA x 100% (for safety) = 320mA Therefore, the dissipated power at the junction is, Pj = (Vin - Vout) (Iout) + (Vin) (Ignd) = (3.465 - 2.45) (320) + (3.465) (2) = 0.3248 + 0.0069 = 0.332 W Assumptions: * * maximum junction temperature = 125C ambient temperature (no airflow) = 70C
Therefore, Tjmax - Tja = Pd x 125 - 70 = 0.332 x = 166 C/W for a 500 mm2 of copper, 60 C/W Pd x = 0.332 x 60 = 19.9C
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Tjmax = Tja + (Pd x ) = 70 + 20 = 90C
2 Therefore, a 500 mm area of copper is sufficient to dissipate the heat.
In the 3.3V Regulator: Using worst case, Vin = 5 + 10% = 5.5V Vout = 3.3 - 5% = 3.135V Iout = 460mA x 100% (for safety) = 920mA Therefore, the dissipated power at the junction is, Pj = (Vin - Vout) (Iout) + (Vin) (Ignd) = (5.5 - 3.135) (920mA) + (5.5) (2509mA) = 2.176 + 1.375 = 3.6 W Assumptions: * * maximum junction temperature = 125C ambient temperature (no airflow) = 70C
Therefore, Tjmax - Tja = Pd x 125 - 70 = 3.6 x = 15.28 C/W for a 5000 mm2 of copper, 15 C/W Pd x = 3.7 x 15 = 55C Tjmax = Tja + (Pd x )
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= 70 + 55 = 125C Therefore, a 5000 mm2 area of copper is sufficient to dissipate the heat.
2 2 2 Therefore, the total copper needed is 5000 mm + 500 mm = 5500 mm . Note that the area of copper on the ground and power planes is more than the required amount.
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6 6.1
PHYSICAL AND MECHANICAL DESCRIPTIONS Form Factor The following figures show the mechanical outline and dimensions of the COMET-QUAD Evaluator Board design. Figure 8: PCI Universal 32-bit Card Mechanical Outline
5.08 Far Side 12 .50 Component -Free Area (Side A Only) 89.53 3.525 Component -Free Area (Both Sides) 10.16 .40
4 .157
(3x) 10.16 .400
106.68 4.200
85.4 3.362
A
B
3.81 .15
4.83 .190
7.5 .295
79.15 3.12 41.2 1.622 56.21 2.213 1/4.63 (Short Card) 6 8/5
(2x) 5.08 .200 5.08 (Short Card Only) .200
12.0 .475
312 (Long Card) 12.283
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6.35 (ISA/EISA) .25 6.48 (MC) .255 1.57 .20 .062 .008 13.62 .536
Cross-hatched area represents the I/O connector window for microchannel and ISA/EISA brackets
81.9 3.224
Note: Clearance unless otherwise noted - 0.127 (.005)
6.1 .240 6.03 .237 12.06 4/5
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Figure 9: PCI Universal 32-bit Card Edge Connector Dimensions and Tolerances
A
56.23 2.23 14.61 .575 12.7 .500 50.17 1.975 (2x) 1.91 .075
62.87 2.475
12.7 .500
Component Side B 1.27 .050
46.35 1.825
44.49 1.750
(4x) 0.927 0.025 0.0365 0.001 48.2 1.90 15.44 .608 63.7 2.508
A
6.1.1 Face Plate The following figure shows the proposed faceplate for the COMET-QUAD Evaluator Board design. Figure 10 - Face Plate
Channel 1
Channel 2
Channel 3
Channel 4 INTB 2.5V 3.3V 5.0V
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6.2
Connectors
6.2.1 Line Interface Connectors Only one set of line interface connectors is provided with the evaluator board. These are the RJ48C connectors. Shielded jacks are used to help reduce EMI radiation and increase EMI tolerance. 6.2.2 System Bus Connector The System Bus Connector allows access to configure the COMET-QUAD and control the external payload loopback. 6.2.3 PCI Edge Connector The PCI Edge Connector is a standard Universal, 32 bit PCI connector. 6.3 LEDs
6.3.1 COMET-QUAD Interrupt LED A PCB mounted LED is connected to the INTB pin to allow for visual indication of interrupts being generated by the COMET-QUAD. * INTB, green - indicates presence of interrupts
6.3.2 Power Status LEDs Three LEDs are provided to display the status of power to the COMET-QUAD board, one for 5.0V, one for 3.3V, and one for 2.5V. * * * +5V, green - indicates presence of +5V +3.3V, green - indicates presence of +3.3V +2.5V; green - indicates presence of +2.5V
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7 7.1
SOFTWARE INTERFACES Memory Map Table 8: System Memory Map PCI9050 Local Address Space CS_0 Address 0000-00FF Device R/W Description COMET-QUAD Registers
PM4354 COMET- R/W QUAD
7.2
PCI 9050 Configuration The following sets of tables specify the values that should be programmed into the SEEP. These values will be loaded into the PCI9050 registers on power-up. Please refer to the PCI9050 datasheet [5] for further details. NOTE: The checksum of the SEEP is 0x230D. Table 9: PCI Local Address Space Register Register PCIIDR PCIREV PCISVID PCIILAR Address 0x000 0x004 0x008 0x00C Description Device_ID/Vendor_ID Class_Code Subsystem_ID/Subsystem_Vendor_ID Maximum Latency MinimumGrant IntPin Routing Value 0x905010B5 0x06800000 0x000311F8 0x00000000
Table 10: PCI Local Address Space Register LAS0RR LAS1RR LAS2RR LAS3RR EROMRR Address 0x010 0x014 0x018 0x01C 0x020 Description Local_Address_Space_0_Range Local_Address_Space_1_Range Local_Address_Space_2_Range Local_Address_Space_3_ Expansion_ROM_Range Value 0x0FFFFC00 0x00000000 0x00000000 0x00000000 0x00000000
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Table 11: PCI Local Address Space Re-Map Register LAS0BA LAS1BA LAS2BA LAS3BA EROMBA Address 0x024 0x028 0x02C 0x030 0x034 Description LocalAddressSpace_0_Base_Addr ess(Re-Map) LocalAddressSpace_1_Base_Addr ess(Re-Map) LocalAddressSpace_2_Base_Addr ess(Re-Map) LocalAddressSpace_3_Base_Addr ess(Re-Map) Expansion_ROM_Base_Address( Re-Map) Value 0x00000001 0x00000000 0x00000000 0x00000000 0x00000000
Table 12: PCI Local Address Space Region Descriptors Register LAS0BRD LAS1BRD LAS2BRD LAS3BRD EROMBR D Address 0x038 0x03C 0x040 0x044 0x048 Description LocalAddressSpace0_Bus_Region _Descriptors LocalAddressSpace1_Bus_Region _Descriptors LocalAddressSpace2Bus_Region_Descriptors LocalAddressSpace3_Bus_Region -Descriptors Expansion_ROM_Bus_Region_De scriptors Value 0x1681A1A0 0x00000000 0x00000000 0x00000000 0x00000000
Table 13: PCI Chip Select Base Register CS0BASE CS1BASE CS2BASE CS3BASE Address 0x04C 0x050 0x054 0x058 Description Chip_Select_0_Base Chip_Select_1_Base Chip_Select_2_Base Chip_Select_3_Base Value 0x00010001 0x00000000 0x00000000 0x00000000
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Table 14: PCI Local Address Space Registers Register INTCSR CNTRL NULL NULL NULL NULL NULL NULL NULL Address 0x05C 0x060 0x064 0x068 0x06C 0x070 0x074 0x078 0x07C Description Interrupt_Control/Status User_I/O| EEPROM|Init_Control Null_data Null_data Null_data Null_data Null_data Null_data Null_data Value 0x00000041 0x00024492 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF
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8
CONFORMANCE SPECIFICATION The Evaluator Board utilizes PCI 9050-1, which is compliant with PCI Local Bus Specification 2.1 [6], supporting low cost slave adapters. The chip allows simple conversion of ISA adapters to PCI. The design of the Evaluator Board, including the external protection circuitry, are designed to meet the major surge immunity and electrical safety standards including FCC Part 68, UL1459 and 1950, and Bellcore TR-NWT-001089. Note that this board has not been tested yet.
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9 9.1
LAYOUT DESCRIPTION Component Placement The overall placement strategies of the components are: * * * * Place the analog circuitry away from the digital circuitry. Keep analog transmit side components separate from the analog receive side components. The PCI Bridge device is placed such that all the PCI interface traces are within the specified length limits of the PCI Rev. 2.1 Specification. The oscillator is placed in a quiet digital section as noise on its power supply will cause jitter on the output, and the oscillator itself generates noise that may affect sensitive analog circuits. All source termination resistors are placed near the outputs and load termination resistors are placed near the inputs. All pull up/down resistors are placed near the output pins. All decoupling capacitors are placed near the power supply pins.
* * *
The overall placement is as follows:
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Figure 12: Main Component Placement Diagram
OSC
RJ48C Line Protection
RJ48C
Line Protection Quad XFRMR
PM4354 COMET -QUAD
RJ48C
Line Protection
RJ48C
Line Protection
PCI Bridge Chip
PCI Edge Connector
9.2
Layer Stacking and Transmission Line Impedance Control The COMET-QUAD Evaluator card has six layers: (from the top down) layer 1 is the top layer for signals, layer 2 for ground, layer 3 for Vcc signals, layer 4 for the 2.5V power plane, layer 5 for the 3.3V power plane and layer 6 is the bottom layer for signals. The dimension of the card conforms to the 5V PCI Raw Short Card, with custom mounting hole locations. The layer configurations are shown below:
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Figure 13: Layer Stack
TOP GND SIG1 2v5 3v3 BOTTOM
Figure 14: PCB Cross Section
w t
1/2 Oz Copper
dielectric r
Ground Plane SIG1
h1 h2 h3 h4 h5 t
dielectric r dielectric r dielectric r
1 Oz Copper 1 Oz Copper 1 Oz Copper
1 Oz Copper
2v5 Plane
3v3 Plane
dielectric r
t
1/2 Oz Copper
where t = relative dielectric constant, nominally 5.0 for G -10 fibre -glass epoxy t = thickness of the copper, fixed according to the weight of copper selected. For 1 oz copper, the thickness is 1.44 mil. For 1/2 oz copper, the thickness is 0.72 mil. This thickness can be ignored if w is large enough.
h1, h2, h3, h4, h5 = thickness of dielectric. w = width of copper
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The PCB related parameters are shown in Table 15: Table 15: PCB parameters Parameters Board Thickness (mil) dielectric thickness between layers 1 and 2 (mil) (h1) dielectric thickness between layers 2 and 3 (mil) (h2) dielectric thickness between layers 3 and 4 (mil) (h3) dielectric thickness between layers 4 and 5 (mil) (h4) dielectric thickness between layers 5 and 6 (mil) (h5) Relative dielectric constant Nominal 62 (including copper thickness) 7 8 24 8 7 4.2
To reduce signal degradation due to reflection and radiation, the traces that carry high speed signals should be treated as micro strip transmission lines with controlled impedance and matched resistive termination. The trace impedance is calculated using the formula: 87 ae 5.98 x h o Zo = x ln e r + 1.41 0.8 x w + t o
Parameter
r
h1 (mil) t (mil) (2 Oz copper) Zo (Ohm) W (mil)
Data 4.2 7 2.88 50 10
Given characteristic impedance Zo, the dielectric thickness h1 is proportional to trace width. A small h1 will result in the traces being too thin to be accurately fabricated. Wider traces can be more precisely manufactured, but they take up too much board space. Therefore, the thickness of the board for a given trace impedance and adequate trace width should be chosen so that the traces take up as little board space as possible yet still leaving enough margin to allow accurate fabrication.
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35
PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
Using the same h1, thickness of copper, and dielectric constant, a 10 mil traces has a characteristic impedance of approximately 50 Ohms while an 3 mil trace has a characteristic impedance of 75 Ohms. We are using controlled impedance of 75 Ohms on this Evaluator Board. 9.3 Power and Ground The following diagrams illustrates the power and ground plane distribution: Figure 15: GND Plane
Ground Plane
Figure 16: VCC Plane
Vcc Plane
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36
PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
Figure 17: 2.5V Plane
2.5V Plane
Figure 18: 3.3V Plane
3.3V Plane
The introduction of ground slots within the ground plane must be avoided as they will increase trace inductance and increase crosstalk. Making clear-out holes too large can accidentally create these slots. 9.4 PCI Bus Signal Specification This layout follows the PCI Rev. 2.1 Specification layout restrictions. The PCI SIG specification has stringent and detailed rules on decoupling, power consumption, trace length limits, routing, trace impedance, as well as signal
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37
PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
loading. Therefore, it is essential to check the latest PCI specification before proceeding with new designs and layouts. The COMET-QUAD Evaluator design board conforms to the following PCI Specification/Recommendations: * * * * * Component height on the component side does not exceed 0.570 inches, and on the solder side does not exceed 0.105 inches. PCI CLK signal trace is 2.5 inches +/- 0.1 inches and is connected to only one load. All 32-bit interface signals have the maximum trace length of 1.5 inches. Trace impedance for shared PCI signals are within 60 - 100 Ohm range, and trace velocity is between 150 and 190 ps/inch. 20 mil wide traces are used to connect the power and ground pins on PCI connector to their respective planes and the trace lengths are limited to 250 mil.
9.5
Routing * * * * All power and ground traces are as wide and short as possible to minimize trace inductance. All high speed traces are routed over continuous image planes (power or ground planes). All traces carrying transmit and receive line rate data should be routed on the same side and kept as short as possible. Both signals of a differential pair are of equal length and routed close to each other.
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38
PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
10
GLOSSARY CompactPCI Compact Peripheral Component Interconnect. A bus standard based on the PCI standard that defines a more rugged mechanical form factor for industrial use. Channel Service Unit. Off-premise T1 interface level provided by CSU. Digital Cross-connect T1 interface level. European First Order transmission format. This is the standardized (ITU-T G.704) base format of the European Pleisosynchronous Digital Hierarchy. It operates at 2.048Mbps. The E1 format consists of frames consisting of 32 octets, or timeslots (numbered 0 to 31). Timeslot 0 alternates between containing an FAS and containing the National Use bits (Sa[8:4]) and an A-bit for RAI. Timeslot 0 also contains an International Use Bit (Si) which can be used to support CRC Multiframe. High Level Data Link Control. A family of bit-oriented protocols providing frames of information with address, control and frame check sequence fields. High Capacity MVIP Multi-Vendor Integration Protocol. A TDM bus standard that is an extension of Mitel's ST-BUS. The MVIP bus is used in computer telephony integration applications. Peripheral Component Interconnect - A bus standard that defines 32 bit transfers over a defined electrical interface. An adapter board for a PCI system which acts as a PCI Master and performs the additional functions of clock distribution and bus arbitration. An adapter board for a PCI system which does not initiate bus transactions. Also known as a slave. Extended Super Frame format.
CSU DS1 DSX-1 E1
HDLC
H-MVIP MVIP
PCI PCI Host
PCI Target ESF
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39
PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
RJ-48C SEEP
An 8 pin RJ-45 modular connector with a standardized pinout used for 100 ohm T1 and 120 ohm E1 interfaces. Serial EEPROM (Electrically Erasable Programmable Read Only Memory) - A type of non-volatile memory which is programmed and read using a serial interface. A level 1 digital trunk operating at 1.544 Mbit/s that is popular in North America and Japan. It is made up of 193 bits, grouped as 1 framing bit followed by 24 DS-0 channels of 8 bits each. A standard specifying a DS1-rate metallic interface, referred to as the network interface (NI), between the network and a customer installation. Time Division Multiplexed - A TDM signal consists of several channels of data which are multiplexed together in time so that a byte (or word, etc.) of one channel of data is transferred, following by a byte of the second, etc.
T1
T1.403
TDM
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
11
REFERENCES
1. PMC-Sierra, Inc., PMC-1990315, "COMET-QUAD Data Sheet", Issue 5, December 2000. 2. PMC-Sierra, Inc., PMC-1970624, "Combined E1/T1 Transceiver Standard Product Datasheet", Issue 9, September 2000. 3. PMC-Sierra, Inc., PMC-1981210, "COMET Reference Design Rev. 2.0", Issue 1, November 1998. 4. PMC-Sierra, Inc., PMC-1980815, "COMET Evaluation Board Rev. 2.0", Issue 4, June 2000. 5. PLX Technology, PCI 9050-1 Data Book, Version 1.01, April 17, 1997. 6. PCI Local Bus Specification Revision 2.1s, June 1, 1995.
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41
PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
12
DISCLAIMER This document is a paper reference design, and as such, has not been built or tested as of this date. Note that the protection circuitry provided in this document has not been tested to date. Therefore, there are no guarantees that it meets FCC Part 68, UL 1459 and 1950, and Bellcore TR-NWT-001089. Please check the PMC-Sierra website regularly for updates to this document.
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42
PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
13
APPENDIX A: BILL OF MATERIALS Table 16: Major Components List Ref. No S1-S16 S17S24 U1 F1-F16 U7 U4 U6 Component P1800SC SIDACtor P0720SC SIDACtor T9021 F1250T Telelink Fuse LM3940 NM93CS46E N PCI-9050 Manufacturer Teccor Electronics 972-580-7777 Teccor Electronics 972-580-7777 Pulse Inc. 619-674-8100 Teccor Electronics 972-580-7777 National Semiconductor 408-721-5000 Fairchild Semiconductor 1-800-364-3577 PLX Technology 800-759-3735 Table 17: Bill of Materials Part Name - Value 1 74HC08_SOICBASE CAPACITOR0.01UF, 50V,X7R_603 Part Number Fairchild Semiconductor MM74HC08M Various U3 Ref Des Qty 1 160 pin PQFP 1 8-pin DIP 1 SOT-223 1 SMD 16 1 DO-214 SMB 8 Package Type DO-214 SMB Quantity 16
2
C4,C10,C12,C13,C15,C17, 32 C19,C20,C22C25,C28,C30,C32,C34,C36, C45,C49,C51,C52,C55C57,C59C61,C65,C66,C68,C70,C71
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
3
CAPACITOR0.1UF,16V, X7R_603
Various
C125 C3,C11,C18,C21,C29,C31, C35,C37,C43,C44,C46C48,C50,C53,C54,C58,C62 -C64,C67,C69,C72 C40 1
4
CAPACITOR0.47UF, 25V,TANT THE CAPACITOR10UF,10V,TANT THE CAPACITOR22UF,6.3V,TANT THE CAPACITOR4.7UF,10V,TANT THE CAPACITOR47UF,6.3V,TANT THE CAPACITOR68UF,6.3V,TANT THE COMETQUAD_PBGABASE
Various
5
Various
C42
1
6
Various
C9,C26,C27
3
7
Various
C5-C8
4
8
Various
C14,C16,C33,C38,C39
5
9
Various
C41
1
10
PMC PM4354-PI
U5
1
11
FUSE SMD - 500A Teccor Electronics - F1-F16 @ F1250T 2X10mailto:FUSE_S MD-500A@2X10 FUSE__SMD_SOC DIGI-KEY -KET-1.000A,SLO- F1303CT-ND BLO F17
16
12
1
13 14 15
HEADER4_100MIL- Sullins Electronics - J7 BASE PZC36SAAN HEADER_4X2_SMT 87267-0850 _2MM-BASE LM3940_SOTBASE LM3940IMP-3.3 J8-J13 U7
1 6 1
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
16 17 18 19
MAX701_SOICBASE MIC39150_T02202.5V
MAXIM MAX701ESA MICREL - MIC39150-2.5BT
U2 U8 Q1 U4
1 1 1 1
MMBT3906_SOT23 MMBT3906LT1 -BASE NM93CS46_DIP8_S Fairchild OCKET-BASE Semiconductor NM93CS46 OSC_TTL_DIP2.048MHZ,50 PPM,CHA P0720SC_SMBBASE SIDACtor P1800SC_SMBBASE SIDACtor PBSWITCH-BASE Pushbutton switch PCI9050_PQFPBASE
20
Champion Y1 K1150BA-2.048MHz MMD MA050T2.048MHz Teccor Electronics P0720SC Teccor Electronics P1800SC PBSWITCH DIGIKEY P8007S-ND PCI9050-1 S17-S24 S1-S16 SW1 U6 P1
1
21 22 23 24 25
8 16 1 1 1
PCI_UNIV_32_CAR EDGE D_CON NCONNECTOR PCI_UNIVA RESISTOR0,5%,603 RESISTOR1,5%,603 RESISTOR100,5%,603 RESISTOR100K,5%,603 RESISTOR10K,1%,603 RESISTOR10M,5%,1206 Various Various Various Various Various Various
26 27 28 29 30 31
R23,R44,R48,R50 R26-R29,R33,R36R38,R42,R43,R45,R47 R3 R30-R32,R46 R6 R5
4 12 1 4 1 1
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
32 33 34 35 36 37 38 39
RESISTOR12.7,1%,603 RESISTOR150,5%,603 RESISTOR18.2,1%,603 RESISTOR330,5%,603 RESISTOR4.7,5%,603 RESISTOR4.7K,5%,603 RESISTOR56,5%,603
Various Various Various Various Various Various Various
R15-R22 R2 R11-R14 R1,R4,R51 R25,R34,R35 R7-R10,R24,R41,R49 R39,R40 RN1-RN13
8 1 4 3 3 7 2 13
RES_ARRAY_4_SM DIGI-KEY -D-4.7K Y44.7KCT-ND Panasonic EXBV8V4K7JV RJ45_SHIELD_UNI STEWART or AMP VERSAL
40 41 42
J1-J4
4 1 1
SSF_LXH5147-LGD LUMEX - D1 SSF-LXH5147LGD TRANSFORMER & PULSE - T9021 DIODE ARRAY T9021_-BASE TEST_POINT_2_PA D60CI R36D-BASE TST_PT-BASE TST_PT_BIGGROUNDED MOUNTING HA DIGIKEY - 36-ND U1
43 44 45
TP9,TP10 S1011- TP3-TP8 TP1,TP2
2 6 2
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PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
14
APPENDIX B: SCHEMATICS The COMET-QUAD Evaluator Board schematics were captured using Cadence software Concept Schematics Capture tool.
14.1
ROOT DRAWING, Sheet 1 This sheet provides an overview of the major functional blocks of the COMETQUAD Evaluator board. It shows interconnections between the COMETQUAD_BLOCK, PCI_INTERFACE_BLOCK, LINE_INTERFACE and POWER blocks.
14.2
COMET-QUAD BLOCK, Sheet 2 This sheet shows the COMET-QUAD device and its power circuitry. The power circuitry includes a Schottky diode for powering up the COMET-QUAD device and separate filtering circuitry for the analog and digital power pins. A LED is connected to the INTB pin to allow for visual indication of interrupts being generated by the COMET-QUAD.
14.3
LINE INTERFACE, Sheet 3 and 4 This sheet shows the termination, magnetics and protection circuitry for the 4 line interfaces. A single diode array and transformers quad module from Pulse is used to couple all of the 4 sets transmit and receive lines of the COMET-QUAD to the connectors. The P1800SC SIDACtor, P0720SC SIDACtor and the F1250T Telelink Fuse provide over voltage and over-current protection. Connections to RJ48C connectors are provided.
14.4
PCI INTERFACE, Sheet 5 This sheet shows the PCI connector and the PCI bridge chip. The PLX PCI9050 PCI bridge chip is compliant to PCI Specification 2.1.
14.5
POWER, Sheet 6 The LM3940 drop-out voltage regulator supplies 3.3V to the COMET-QUAD device. Three LED's are provided to display the status of power to the COMETQUAD board, one for 5.0V, one for 3.3V, and one for 2.5V.
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47
10
9
8
7
6
5
4
3
2
1
REVISIONS
NOTE: VCC = +5.0V ZONE REV DESCRIPTION DATE APPR
H
H
G
G
P6 POWER
INTB F F
P5 PCI_INTERFACE E INTB CSB RDB WRB D<7..0> A<10..0> D<7..0> A<10..0>
P2 COMET_QUAD_BLOCK INTB CSB RDB WRB D<7..0> A<10..0> TXTIP<4..1> TXRING<4..1> TXCM<4..1> RXTIP<4..1> RXRING<4..1>
P3-4 LINE_INTERFACE E TXTIP<4..1> TXRING<4..1> TXCM<4..1> RXTIP<4..1> RXRING<4..1>
TXTIP<4..1> TXRING<4..1> TXCM<4..1> RXTIP<4..1> RXRING<4..1>
RESETB TMS TDI TDO TRSTB TCK
RESETB TMS TDI TDO TRSTB TCK
D
D
C
C
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=COMET_QUAD_KIT_ROOT ABBREV=COMET_QUAD_KIT_ROOT LAST_MODIFIED=Wed Nov 15 14:00:44 2000 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-1991237 DOCUMENT ISSUE NUMBER: 2.0 TITLE: COMET QUAD EVALUATOR DESIGN ROOT DRAWING ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE DATE: NOV 2000 REVISION NUMBER: 3 PAGE:1 TRUE 1 OF 6 A
10
9
8
7
6
5
4
3
2
1
2F6> 2F6> 2F6<> 2E6>
COMET-QUAD BACKPLANE CHANNEL #1 J11 BRCLK<1> BTCLK<1> 1 2 2F10<> BRSIG<1> BTSIG<1> 3 4 2F10< BRFP<1> BTFP<1> 5 6 2F10<> BRPCM<1> BTPCM<1> 7 8 2E10<
HEADER 4X2
REVISIONS
NOTE: VCC = +5.0V ZONE REV DESCRIPTION DATE APPR
H
H
2F6> 2F6> 2F6<> 2E6>
COMET-QUAD BACKPLANE CHANNEL #2 J8 BRCLK<2> BTCLK<2> 1 2 2F10<> BRSIG<2> BTSIG<2> 3 4 2F10< BRFP<2> BTFP<2> 5 6 2F10<> BRPCM<2> BTPCM<2> 7 8 2E10<
HEADER 4X2
TRANSMIT ANALOG POWER DECOUPLING 1 3.3 V 3.3 V
1 R45 0.1UF C53 0.01UF C52
RECEIVE ANALOG POWER DECOUPLING 1 & 2 3.3 V
1 R47 0.1UF C67 0.01UF C66
3.3 V
1 R36 0.1UF C31 0.01UF C28
3.3 V
1 R42 0.1UF C50 0.01UF C51
3.3 V
1 R29 0.1UF C21 0.01UF C20
3.3 V
1 R43 0.1UF C69 0.01UF C65
3.3 V
1 R26
QUIET ANALOG POWER DECOUPLING 1 & 2 3.3 V 3.3 V
2F6> 2F6> 2F6<> 2E6>
COMET-QUAD BACKPLANE CHANNEL #3 J10 1 2 BRCLK<3> BTCLK<3> 2F10<> 3 4 BRSIG<3> BTSIG<3> 2F10< BRFP<3> BTFP<3> 5 6 2F10<> BRPCM<3> BTPCM<3> 7 8 2E10<
HEADER 4X2
1 R33 0.1UF C29 0.01UF C30
R34
4.7
C18 0.01UF C19
22UF C26 0.01UF C24
4.7
R25 22UF
0.1UF
G
G
C9 0.01UF C15
2F6> 2F6> 2F6<> 2E6>
COMET-QUAD BACKPLANE CHANNEL #4 J9 1 2 BRCLK<4> BTCLK<4> 2F10<> 3 4 BRSIG<4> BTSIG<4> 2F10< 5 6 BRFP<4> BTFP<4> 2F10<> BRPCM<4> 7 8 BTPCM<4> 2E10< PBGA U5
HEADER 4X2
2H7<> 2G7<>
BTCLK<4..1>
COMET-QUAD PM4354 1 OF 4
4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 2 4 6 8 M14 L2 H16 F3 M15 M3 J14 G3 N13 M1 H14 H4 M16 M4 H13 F4 K2 K1 L4 K3 F1 F2
BRCLK<4..1> BRCLK<4> BRCLK<3> BRCLK<2> BRCLK<1> BRSIG<4> BRSIG<3> BRSIG<2> BRSIG<1> BRFP<4> BRFP<3> BRFP<2> BRFP<1>
N16 N1 F16 E2 P16 P2 G15 E3 P15 R1 G14 E4 N15 P1 F13 E1 4 3 2 1
BTCLK<4> BTCLK<3> BTCLK<2> BTCLK<1> BTSIG<4> BTSIG<3> BTSIG<2> BTSIG<1> BTFP<4> BTFP<3> BTFP<2> BTFP<1> BTPCM<4> BTPCM<3> BTPCM<2> CASBTD_BTPCM<1>
2G9< 2H9<
F
2H8> 2G8>
BTSIG<4..1>
BRSIG<4..1>
4 3 2 1
2G9< 2H9<
F
2H7<> 2G7<>
BTFP<4..1>
BRFP<4..1>
4 3 2 1
2G9<>2H9<>
TRANSMIT ANALOG POWER DECOUPLING 2 & 3 3.3 V 3.3 V 3.3 V 3.3 V
2H8> 2G8>
BTPCM<4..1>
BRPCM<4..1>
4 3 2 1
J12 GND E
1 3 5 7
BRPCM<4> BRPCM<3> BRPCM<2> CASBRD_BRPCM<1>
2G9< 2H9<
1 R37 1 R28 47UF C16 0.01UF C17 1 R38 47UF C33 0.01UF C32 1 R27 47UF C14 0.01UF C49
CCSBTD MVBTD MVBRD_CCSBRD CMV8MCLK
HEADER 4X2
CMVFPC CMVFPB
CCSBTD MVBTD MVBRD_CCSBRD CMV8MCLK CMVFPC CMVFPB SYSTEM PBGA U5
47UF C38 0.01UF C70
E PBGA U5
R14 C8
3G10< 3D10< 4G10< 4D10<
TXTIP<4..1>\I
4 3 2 1
R13 P4 A13 B4 T11 R6 A11 B6
COMET-QUAD PM4354 TXTIP1<4> 2 OF 4 RXTIP<4> TXTIP1<3> RXTIP<3> TXTIP1<2> RXTIP<2> TXTIP1<1> RXTIP<1> TXTIP2<4> TXTIP2<3> TXTIP2<2> TXTIP2<1> TXRING1<4> TXRING1<3> TXRING1<2> TXRING1<1> TXRING2<4> TXRING2<3> TXRING2<2> TXRING2<1> TXCM<4> TXCM<3> TXCM<2> TXCM<1> RXRING<4> RXRING<3> RXRING<2> RXRING<1> RVREF<4> RVREF<3> RVREF<2> RVREF<1> RES<8> XCLK CTCLK RSYNC PIO RES<7> RES<6> RES<5> RES<4> RES<3> RES<2> RES<1>
N10 P7 D10 C7 P10 T7 C10 A7 P9 T8 C9 A8 T15 J13 L16 R16 R15 T16 P8 D8 J4 J15 N3 L14
4 3 2 1 4 3 2 1
RXTIP<4..1>\I
QAVD<2> QAVD<1>
COMET-QUAD PM4354 4 OF 4 QAVS<2> QAVS<1> RAVS1<4> RAVS1<3> RAVS1<2> RAVS1<1> RAVS2<4> RAVS2<3> RAVS2<2> RAVS2<1> TAVS1<4> TAVS1<3> TAVS1<2> TAVS1<1> TAVS2<4> TAVS2<3> TAVS2<2> TAVS2<1> TAVS3<4> TAVS3<3> TAVS3<2> TAVS3<1> VSSC2_5<7> VSSC2_5<6> VSSC2_5<5> VSSC2_5<4> VSSC2_5<3> VSSC2_5<2> VSSC2_5<1> VSS3_3<9> VSS3_3<8> VSS3_3<7> VSS3_3<6> VSS3_3<5> VSS3_3<4> VSS3_3<3> VSS3_3<2> VSS3_3<1> VSSQ3_3<2> VSSQ3_3<1> GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 POWER
T14 D9 R9 N7 A9 D7 R10 N6 B10 D6 N11 P6 D11 C6 R12 N4 B12 C4 T12 R5 A12 B5 L15 K16 G13 L3 J3 H1 G2 C14 M2 P14 L13 F14 R2 J2 D1 B2 K13 G4 J7 J8 J9 J10 K7 K8 K9 K10
3C10> 3F10> 4C10> 4F10>
T9 R8 B9 B8
RXRING<4..1>\I
RAVD1<4> RAVD1<3> RAVD1<2> RAVD1<1> RAVD2<4> RAVD2<3> RAVD2<2> RAVD2<1> TAVD1<4> TAVD1<3> TAVD1<2> TAVD1<1> TAVD2<4> TAVD2<3> TAVD2<2> TAVD2<1> TAVD3<4> TAVD3<3> TAVD3<2> TAVD3<1> VDDC2_5<8> VDDC2_5<7> VDDC2_5<6> VDDC2_5<5> VDDC2_5<4> VDDC2_5<3> VDDC2_5<2> VDDC2_5<1> VDD3_3<6> VDD3_3<5> VDD3_3<4> VDD3_3<3> VDD3_3<2> VDD3_3<1> VDDQ3_3<2> VDDQ3_3<1> CAVS CAVD GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
3B10> 3E10> 4B10> 4E10>
T10 R7 A10 B7
D
3F10< 3D10< 4F10< 4D10<
TXRING<4..1>\I
4 3 2 1
T13 R4 C13 A3 R11 N5 B11 D5
VCC Y1 RES[8] CTCLK RSYNC PIO RES[6] RES[5] RES[4] RES[3] RES[2] RES[1]
1 3 5 7 R23 56 R39 R30 100K 56 R40 8
P11 T6 C11 A6 P13 T4 D13 A4 P12 T5 C12 A5 J16 M13 K15 H15 L1 J1 H3 G1 N14 G16 N2 K4 D4 C3 K14 H2 N8 N9 G7 G8 G9 G10 H7 H8 H9 H10
D
OSC_TTL OUT VCC GND 2.048MHZ 50 PPM
C56 14
C58
0.01UF 0.1UF 7
3G10> 3D10> 4G10> 4D10>
TXCM<4..1>\I
4 3 2 1
N12 P5 D12 C5
C22 0.01UF R32 100K
LINE C PBGA U5 COMET-QUAD PM4354 3 OF 4 D<7> A<10> A<9> D<6> A<8> D<5> A<7> D<4> A<6> D<3> A<5> D<2> A<4> D<1> A<3> D<0> A<2> A<1> A<0> RDB WRB CSB TDO TDI ALE TCK INTB TMS RSTB TRSTB MICRO_JTAG
J13
2 4 6 8
C25 0.01UF R46 100K C57 0.01UF R31 100K 4.7
3.3 V 2.5 V
R35
0
C
HEADER 4X2
D3 D2 C2 C1 B1 A1 A2 B3 D14 E15 E16 E14 F15 E13 7 6 5 4 3 2 1 0
5E2>
A<10..0>\I
10 9 8 7 6 5 4 3 2 1 0 D15 D16 C16 C15 B16 A16 B15 A15 B14 A14 B13 T1 T3 T2 R3 P3
22UF C27
3.3 V
D<7..0>\I 3.3 V
5G2<>
1 1
TP10 TP9
C23 0.01UF
0.01UF C60
0
R48 0
R44
4.7K
R41
RESETB\I VCC
4.7K
5C2>
5C2< 6F10<
3
74HC08
1 2
R9
B
5H5< 5H5> 5H5> 5H5>
TDO\I TDI\I TCK\I TMS\I
RDB\I WRB\I CSB\I
5C2> 5C2> 5C2>
SOIC U3 INTB\I
8 6 5
VCC RESET
U2 MR
PB4 SW1
1 4 3
PBSWITCH
1 2
B
SOIC U3
4 6
74HC08
RESET GND MAX701
4
5
TRSTB\I
5H5>
SOIC U3
9 8
74HC08
PMC-Sierra, Inc.
DOCUMENT NUMBER: PMC-1991237 DOCUMENT ISSUE NUMBER: 2.0 TITLE: COMET QUAD EVALUATOR DESIGN COMET QUAD ENGINEER: PMC-SIERRA, INC. (WT) ISSUE DATE: NOV 2000 REVISION NUMBER: 3 PAGE:2 TRUE 1 OF 6 A
10
A
11
SOIC U3
12
74HC08
DRAWING TITLE=COMET_QUAD_BLOCK ABBREV=COMET_QUAD_BLOCK LAST_MODIFIED=Mon Nov 20 14:42:55 2000
13
10
9
8
7
6
5
4
3
2
10
9
8
7
6
5
4
3
2
1
REVISIONS
NOTE: VCC = +5.0V ZONE REV DESCRIPTION DATE APPR
H
H
2E10>
TXTIP<1>\I
1 12.7 R22
F16 500A@2X10 G
G
12.7
C8 R21
1
1:2.42
40
S19
2
S15 F15
2
2D10>
TXRING<1>\I
3
38
12
2D10<
TXCM<1>\I
4.7UF
U1
T9021
S16
1
500A@2X10 3.3 V
2 1 2 3 4 5 6 7 8 11 12
UNIVERSAL J1 1 2 3 4 5 6 7 8
SHIELD1 SHIELD2
F F14
7 1 1
F
500A@2X10
S14
12
2E6<
RXTIP<1>\I
18.2 4 R14
13 14
1:2.42
S20
37 2
RJ45_SHIELD S13 F13
2
2D6<
RXRING<1>\I
5
36
500A@2X10
E E
2E10>
TXTIP<2>\I
12.7 R20 1
F12 500A@2X10 D
12 2
D
2D10<
TXCM<2>\I
12.7 R19
4.7UF C7 6
1:2.42
S21
35
1
S12
S11 F11
2
2D10>
TXRING<2>\I
8
33
500A@2X10
UNIVERSAL J2 F10 C
1 1 2 3 4 5 6 7 8 11 12
500A@2X10
S10
12
1 2 3 4 5 6 7 8
SHIELD1 SHIELD2
C
2E6<
RXTIP<2>\I
18.2 9 R13
1
S22
1:2.42
32 2
13 14
S9 F9
2
RJ45_SHIELD 500A@2X10
2D6<
RXRING<2>\I
10
31
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE_INTERFACE LAST_MODIFIED=Mon Nov 20 14:42:39 2000 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-1991237 DOCUMENT ISSUE NUMBER: 2.0 TITLE: COMET QUAD EVALUATOR DESIGN LINE INTERFACE 1/2 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE DATE: NOV 2000 REVISION NUMBER: 3 PAGE:3 TRUE 1 OF 6 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
NOTE: VCC = +5.0V ZONE REV DESCRIPTION DATE APPR
H
H
2E10>
TXTIP<3>\I
1 12.7 R18
F8 500A@2X10 G
G
12.7
C6 R17
11
1:2.42
S23
30 2
S7 F7
2
2D10>
TXRING<3>\I 3.3 V
13
28
12
2D10<
TXCM<3>\I
4.7UF
U1
T9021
1
S8
500A@2X10 UNIVERSAL J3
1 2 3 4 5 6 7 8 11 12
12
F F6
17 1
500A@2X10
S6
1 14 R12
1 2 3 4 5 6 7 8
SHIELD1 SHIELD2
F
18.2
1:2.42
S24
27 2
12
2E6<
RXTIP<3>\I S5
13 14
RJ45_SHIELD F5
2
2D6<
RXRING<3>\I
15
26
500A@2X10
E E
2E10>
TXTIP<4>\I
12.7 R16 1
F4 500A@2X10 D
12 2
1
D
2D10<
TXCM<4>\I
12.7 R15
4.7UF C5 16
S4
S18
1:2.42
25
S3 F3
2
2D10>
TXRING<4>\I
18
23
500A@2X10 UNIVERSAL J4 F2 C
1 1 2 3 4 5 6 7 8 11 12
500A@2X10
S2
12
2E6<
RXTIP<4>\I
18.2 19 R11
1 2 3 4 5 6 7 8
SHIELD1 SHIELD2
C
1
S17
1:2.42
22 2
13 14
S1 RJ45_SHIELD F1
2
2D6<
RXRING<4>\I
20
21
500A@2X10
B
B
PMC-Sierra, Inc.
A DRAWING TITLE=LINE_INTERFACE ABBREV=LINE_INTERFACE LAST_MODIFIED=Mon Nov 20 14:42:41 2000 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-1991237 DOCUMENT ISSUE NUMBER: 2.0 TITLE: COMET QUAD EVALUATOR DESIGN LINE INTERFACE 2/2 ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE DATE: NOV 2000 REVISION NUMBER: 3 PAGE:4 TRUE 1 OF 6 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
NOTE: VCC = +5.0V
TDI\I TMS\I TRSTB\I TCK\I TDO\I
2B10< 2B10< 2A4< 2B10< 2B10>
ZONE
REV
DESCRIPTION
DATE
APPR
H
VCC P1
A1 A2 A3 A4 A5 A6 A7 A8
VCC
H
TRST# +12V TMS TDI +5V INTA# INTC# +5V RESERVED +VI/O RESERVED
-12V TCK GROUND TDO +5V +5V INTB# INTD# PRSNT1# RESERVED PRSNT2#
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
U6 VDD<1> VDD<2> VDD<3> VDD<4> VDD<5> VDD<6> VDD<7> VDD<8> VDD<9> VDD<10>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 43 42 39 38 37 36 35 34 32 31 30 29 28 25 24 23 11 8 7 6 5 4 3 2 157 156 155 154 153 152 151 150 33 22 12 158 21 13 14 15 17 159 16 19 20 149 148 44 18 144 143 145 142 1 2 3 4 1 10 27 41 50 66 81 103 121 146 91 90 89 88 87 86 85 84 83 82 79 78 77 76 75 74 73 72 71 70 69 62 61 60 59 58 57 56 55 54 53 52 92 93 94 95 96 97 98 100 101 102 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 122 49 48 47 46 137 136 135 134 133 132 63 130 131 138 139 140 141 123 124 127 126 125 128 129 64 68
VCC VCC G RN13 5 4.7K 4 RN12 5
6 7 8 6 7 8 3 2 1
G
A9 A10 A11
7 6 5 4
4 3 2 1
3 2 1 0
4.7K
D<7..0>\I
2C8<>
A14 A15 A16 A17 A18
3.3VAUX RST# +VI/O GNT# GROUND PME# AD[30] +3.3V AD[28] AD[26] GROUND AD[24] IDSEL +3.3V AD[22] AD[20] GROUND AD[18] AD[16] +3.3V FRAME# GROUND TRDY# GROUND STOP# +3.3V RESERVED RESERVED GROUND PAR AD[15] +3.3V AD[13] AD[11] GROUND AD[09]
RESERVED GROUND CLK GROUND REQ# +VI/O AD[31] AD[29] GROUND AD[27] AD[25] +3.3V C/BE[3]# AD[23] GROUND AD[21] AD[19] +3.3V AD[17] C/BE[2]# GROUND IRDY# +3.3V DEVSEL# GROUND LOCK# PERR# +3.3V SERR# +3.3V C/BE[1]# AD[14] GROUND AD[12] AD[10] GROUND
B14 B15 B16 B17 B18 B19
PCICLK
F
30
A19 A20 A21 28 26 A22 A23 A24 24 A25 A26 A27
AD<31..0>
B20 B21 29 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 12 10 4.7K R7 4.7K R8 14 1 17 2 21 19 23 3 27 25 31
CBE<3..0>
E
22 20
A28 A29 A30
18 16
A31 A32 A33 A34 A35 A36 A37 A38
AD<0> AD<1> AD<2> AD<3> AD<4> AD<5> AD<6> AD<7> AD<8> AD<9> AD<10> AD<11> AD<12> AD<13> AD<14> AD<15> AD<16> AD<17> AD<18> AD<19> AD<20> AD<21> AD<22> AD<23> AD<24> AD<25> AD<26> AD<27> AD<28> AD<29> AD<30> AD<31> C/BEB<0> C/BEB<1> C/BEB<2> C/BEB<3> PAR FRAMEB IRDYB TRDYB STOPB IDSEL DEVSELB PERRB SERRB CLK RSTB INTAB LOCKB EESK EEDO EEDI EECS TEST VSS<1> VSS<2> VSS<3> VSS<4> VSS<5> VSS<6> VSS<7> VSS<8> VSS<9> VSS<10>
D
A39 A40 A41 A42 A43 15 A44 A45 13 11 A46 A47 A48
U4 NM93CS46
99 9 26 40 51 65 80 104 120 147 160
VCC PRE PE GND
VCC
C
9 A49
0
A52 A53 6 4 A54 A55 A56 2 0 A57 A58 A59 A60 A61 A62
C/BE[0]# +3.3V AD[06] AD[04] GROUND AD[02] AD[00] +VI/O REQ64# +5V +5V
AD[08] AD[07] +3.3V AD[05] AD[03] GROUND AD[01] +VI/O ACK64# +5V +5V
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
8 7
5 3
LAD<0> LAD<1> LAD<2> LAD<3> LAD<4> LAD<5> LAD<6> LAD<7> LAD<8> LAD<9> LAD<10> LAD<11> LAD<12> LAD<13> LAD<14> LAD<15> LAD<16> LAD<17> LAD<18> LAD<19> LAD<20> LAD<21> LAD<22> LAD<23> LAD<24> LAD<25> LAD<26> LAD<27> LAD<28> LAD<29> LAD<30> LAD<31> LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LBEB<0> LBEB<1> LBEB<2> LBEB<3> LINTI1 LINTI2 LCLK LHOLD LHOLDA LRESETB BCLKO CSB<0> CSB<1> USER0/WAITOB USER1/LLOCKOB USER2/CS2B USER3/CS3B ADSB BLASTB LWR RDB WRB LRDYIB BTERMB ALE MODE
0 1 2 3 4 5 6 7 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8 5 6 7 8
VCC
4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1
RN1 4.7K RN2 4.7K RN3 4.7K RN4 4.7K
1 RN11 8
F
VCC
4.7K 1 RN10 8
4.7K RN9
3 22 13 04
7 62 53 44
RN6 4.7K
0 1 2 3 4 5 6 7 8 9 10
1 102 93 84
4.7K A<10..0>\I
RN5 4.7K
7 6 5
7 6 5
8 7 6 5
2C10<
E
D VCC
7 5 6 8
CS SK DI DO
4.7K
R24
2 4 3 1
4.7K
RN8
INTB\I
2B7>
R50 0
RESETB\I CSB\I VCC
7 8 6 5
2B4< 2B8<
8 7 6 5
C
2 1 3 4
4.7K
RN7
RDB\I WRB\I
2B8< 2B8<
4.7K
R49 4.7K
1
R10
PCI-9050-1
B
B
PCI_UNIV_32BIT_CARD_CONNECTOR
PMC-Sierra, Inc.
A DRAWING TITLE=PCI_INTERFACE ABBREV=PCI_INTERFACE LAST_MODIFIED=Mon Nov 20 14:42:49 2000 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-1991237 DOCUMENT ISSUE NUMBER: 2.0 TITLE: COMET QUAD EVALUATOR DESIGN PCI INTERFACE ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE DATE: NOV 2000 REVISION NUMBER: 3 PAGE:5 TRUE 1 OF 6 A
10
9
8
7
6
5
4
3
2
1
REVISIONS
NOTE: VCC = +5.0V ZONE REV DESCRIPTION DATE APPR
H
H
G VCC
G
47UF
C39
+
F VCC
2
F VCC
MMBT3906 0.01UF C45 0.01UF C4 0.01UF C59 0.01UF 0.1UF C63 0.1UF C46 0.1UF C44 0.1UF
VCC
PLACE ONE CAP FOR MAX701 DEVICE VCC
PLACE ONE CAP FOR HC08 DEVICE VCC
PLACE ONE CAP FOR NM93CS46 DEVICE VCC
2B7>
INTB\I
10K R6
1 3
3.3 V
2.5 V
330 100 150 330 R4 R3 R2 R1 A1 A2 A3 A4
GREEN D1
K1 K2 K3 K4 LED SSF-LXH5147
E
PLACE ONE CAP ON EACH SIDE OF THE PCI9050 DEVICE
C48
PLACE ONE CAP ON EACH SIDE OF THE PCI9050 DEVICE
C61
C1 0.1UF
C3 0.1UF
C2 0.1UF
E
VCC F17
1
SOT223 U7
LM3940 VIN VOUT GND TAB
2 3 4
3.3 V
1
U8 IN
TO220 OUT GND TAB
2 3
2.5 V 3.3 V
C43 0.1UF 330 R51 C42 10UF
3.3 V
1.0A
C40 0.47UF
MIC39150
C41 68UF 4
2.5V
C72 0.1UF
C62 0.1UF
C64 0.1UF
C47 0.1UF
C71 0.01UF
C55 0.01UF
C34 0.01UF
C13 0.01UF
D
PLACE ONE CAP PER TWO 3.3V DIGITAL POWER PIN ON THE COMET QUAD
PLACE ONE CAP PER TWO 3.3V DIGITAL POWER PIN ON THE COMET QUAD
D
2.5 V
2.5 V
C35 0.1UF
C54 0.1UF
C11 0.1UF
C37 0.1UF
C36 0.01UF
C10 0.01UF
C12 0.01UF
C68 0.01UF
2.5 V C
3.3 V
VCC
1 2 3 4
100MIL J7 P_1 P_2 P_3 P_4 HEADER4
TP2 GROUNDED MOUNTING HOLE T TP1 GROUNDED MOUNTING HOLE T
10M R5
PLACE ONE CAP PER TWO 2.5V DIGITAL POWER PIN ON THE COMET QUAD
PLACE ONE CAP PER TWO 2.5V DIGITAL POWER PIN ON THE COMET QUAD
C
TP5 T TP6 T TP7 T TP8 T TP3 T B TP4 T
B
PMC-Sierra, Inc.
A DRAWING TITLE=POWER ABBREV=POWER LAST_MODIFIED=Mon Nov 20 14:42:44 2000 10 9 8 7 6 5 4 3 DOCUMENT NUMBER: PMC-1991237 DOCUMENT ISSUE NUMBER: 2.0 TITLE: COMET QUAD EVALUATOR DESIGN POWER ENGINEER: PMC-SIERRA, INC. (WT) 2 ISSUE DATE: NOV 2000 REVISION NUMBER: 3 PAGE:6 TRUE 1 OF 6 A
PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
15
APPENDIX C: LAYOUT
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
48
PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
NOTES
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
49
PRELIMINARY EVALUATOR BOARD PMC-1991237 ISSUE 2
PM4354 COMET-QUAD
COMET-QUAD EVALUATOR BOARD
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-1991237 (P2) Issue date: January 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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